Tag Archives: Computer Architecture
Protected: 12 – CPU Performance: Unfolded Data Flow Paths
Protected: 11 – Controller Specification
Lab 05
ROM8x4.dwv
library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_arith.all; entity ROM8x4 is port (addr : in std_logic_vector(2 downto 0); data : out std_logic_vector(3 downto 0)); end ROM8x4; architecture behav of ROM8x4 is type memory is array (0 to 7) of std_logic_vector(3 downto 0); begin process is variable ROM : memory; begin ROM(0) := "0011"; ROM(1) := "1010"; ROM(2) := "0000"; wait for 10 ns; data <= ROM( to_integer(addr) ); wait on addr; end process; end behav;
RF8x4.dwv
library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_arith.all; entity RF8x4 is port (ld, clk : in std_logic; a_addr, b_addr, d_addr : in std_logic_vector(2 downto 0); d : in std_logic_vector(3 downto 0); a, b : out std_logic_vector(3 downto 0)); end RF8x4; architecture behav of RF8x4 is type memory is array (0 to 7) of std_logic_vector(3 downto 0); begin process is variable R : memory; variable d_index : natural; begin if clk = '1' then case ld is when '1' => d_index := to_integer(d_addr); R(d_index) := d; a <= R( to_integer(a_addr) ); b <= R( to_integer(b_addr) ); when '0' => end case; end if; wait for 10 ns; end process; end behav;
Circuit Diagram
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