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Lab 05

ROM8x4.dwv

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;

entity ROM8x4 is
    port (addr : in std_logic_vector(2 downto 0);
          data : out std_logic_vector(3 downto 0));
end ROM8x4;

architecture behav of ROM8x4 is
type memory is array (0 to 7) of std_logic_vector(3 downto 0);
begin
	process is
	variable ROM : memory;
	begin
		ROM(0) := "0011";
		ROM(1) := "1010";
		ROM(2) := "0000";

		wait for 10 ns;
		data <= ROM( to_integer(addr) );
		wait on addr;
	end process;

end behav;

RF8x4.dwv

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;

entity RF8x4 is
    port (ld, clk : in std_logic;
    	  a_addr, b_addr, d_addr : in std_logic_vector(2 downto 0);
          d : in std_logic_vector(3 downto 0);
          a, b : out std_logic_vector(3 downto 0));
end RF8x4;

architecture behav of RF8x4 is
type memory is array (0 to 7) of std_logic_vector(3 downto 0);
begin
	process is
	variable R : memory;
	variable d_index : natural;
	begin
		if clk = '1'
		then case ld is
				when '1' =>
					d_index := to_integer(d_addr);
					R(d_index) := d;
					a <= R( to_integer(a_addr) );
					b <= R( to_integer(b_addr) );
 				when '0' =>
			end case;
		end if;
		wait for 10 ns;
	end process;

end behav;

Circuit Diagram

Reading List

Week 1-2: Review

  • Appendix C (CD-ROM): Sections C.1 to C.4, C.7, C.8 (to middle of page C-54), C.10, C.11
    • Problems (pg C-80): C.3, C.5, C.11, B.18, B.19, C.20, C.21 (Use VHDL rather than Verilog), C.35, C.37, C.38, C.39
  • Ashendon’s “Student’s Guide to VHDL”, Chapter 1

Week 3-6: State machine diagrams, instruction set architectures, and intro to simple CPU design

  • Chapter 2, Sections 2.1 to 2.5
    • Problems (pg 180): 2.1 (1, 2, 3), 2.4 (1, 2, 3), 2.7, 2.10
  • Chapter 3, Section 3.2, 3.3, 3.5
    • Problems (pg 283): 3.2, 3.3, 3.10, 3.11.2, 3.14.4
  • Appendix C, Section C.8:”Register Files”
  • Chapter 4, Sections 4.1 to 4.4
    • Problems (pg 409): 4.1, 4.7, 4.9, 4.10, 4.11

Week 7-10: CPU performance and memory organization

  • Chapter 4, Sections 4.5 to 4.8
    • Problems (pg 409): 4.12, 4.13
  • Appendix C, Section C.9
  • Chapter 5, Sections 5.1 to 5.3
    • Problems (pg 548): 5.3, 5.4

Week 11-13: Intro to virtual memory and I/O interfaces

  • Chapter 5, Section 5.4, 5.5
  • Chapter 6, Sections 6.1, 6.3, 6.5 and 6.6.